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| High performance processor architecture projects A Primer on Processor Architecture and Fast Benchmarking A. Hossain, "Processor Architecture and Fast Benchmarking: A Primer ", Colloquium at the TOBB University of Economics and Technology, Ankara, Turkey, May 2011. <PDF> Fast Benchmarking for Processor Design Architecture simulations may take days during design when silicon is not available. Long simulation time is impractical, yet the cost of early design mistake is high. Hence, fast architectural parameter exploration without rigorous simulation is an important problem. Analytical models can execute fast. However, few analytical models can produce benchmark performance of a design. The presented method, termed Fast Benchmarking, based on analytical models, can produce benchmark performance of a processor in a few hundred milliseconds. With accurate model, performance data produced by the tool is accurate. For example, instruction fetch results differ by ±7% on average with simulations. This paper further extends the concept by presenting a new method for analytically guided adaptive architecture simulation. To our knowledge, no other work has presented a full methodology to use analytical models for the study of processor performance during design. The method gives birth to a valuable tool that can be used in the industry for designing high performance multi-core, multi-threaded processors. A. Hossain, D. Pease, J. Burns, "Fast Benchmarking for Processor Design", International Journal of Modelling and Simulation, Vol. 32, No. 1, 2012. <PDF> Trace Cache Miss Rate Trace Cache is a hardware mechanism to improve instruction fetch performance of a processor. Analytical model of Trace Cache Miss Rate is rare. This paper presents perhaps the first of its kind. The model is used in the Fast Benchmarking methodology. A. Hossain, D. Pease, A. El Kateeb, "Trace Cache Miss Rate ", International Journal of Modeling and Simulation, vol. 27, no. 3, 2007 <PDF> A Mathematical Model of Trace Cache An earlier more comprehensive version of the Trace Cache models presented in this paper. A. Hossain, D. Pease, J. Burns, N. Parveen, "A Mathematical Model of Trace Cache", IEEE International Conference on Application Specific Architectures (ASAP 2002), p151-162, San Jose, 2002.<PDF> Trace Cache Performance Parameters This paper presents the performance parameters, and an analytical model of the Trace Cache instruction fetch performance. A. Hossain, D. Pease, J. Burns, N. Parveen, "Trace Cache Performance Parameters", IEEE Int Conf. Computer Design, ICCD 2002, Freiburg, Germany, <PDF> |
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